The present invention relates to an access arbitration system to several processors or microprocessors having a common bus. The invention is applied more particularly to the management of the accesses to several microprocessors or processors having common resources, such as e.g. memories.
In the processor field, an important problem which has been solved in a more or less satisfactory manner, is that of access by several processors to common resources by means of a common bus. This problem has become increasingly important with the event of microprocessors because, in view of their relatively high power, cost and greater overall dimensions, it is of greater importance to design multiprocessor systems and to give them access to common resources by means of a common bus.
It is known that this type of access requires an arbitration, as a function of the priority criteria of the access requests made by the processors. It is also known to operate a multiprocessor system in either a synchronous or an asynchronous manner.
In a multiprocessor system operating in a synchronous manner, all the processors are controlled by the same clock. In this type of system, the length of the buses giving access to the common resources via a common bus is an important parameter because the different multiprocessors must function in a synchronous manner and the length of the buses acts on the synchronism. Another problem involved in the design of a multiprocessor system with a common clock is that of phase lags to the common clock during pulse paths thereof in the different buses and circuits. The main disadvantage of such synchronous systems is that the system availability is closely linked with the common clock cycle.
In multiprocessor systems where the processors operate in an asynchronous manner, synchronization thereof only occurs during accesses to the common resources. In an asynchronous system, it is possible to add a processor to the existing system without having to modify the algorithms controlling the arbitration of the access requests of the various processors having a common bus. Thus, asynchronous multiprocessor systems have important advantages compared with synchronous systems.
Apart from the fact that multiprocessor systems can operate either synchronously or asynchronously, another essential difference between these different systems is in the arbitration systems for the access request of the different processors to common resources, by means of a common bus. Among the different arbitration systems which can be used, it is necessary to distinguish between "series" arbitration systems and "parallel" arbitration systems.
In series arbitration systems, each processor comprises an arbitration circuit, whose output is connected to the input of the immediately lower priority arbitration circuit. Thus, the different arbitration circuits are connected in line and these systems require the use of a clock, which manages the access requests of the different processors with a common bus and which also manages the results of the bus of the operations carried out by the different processors. Thus, the number of processors which can be grouped by using series arbitration systems is dependent on the frequency of the common clock and the time lags introduced into the multiprocessor system by the priority operations carried out by the arbitration systems. With the present state of the art, a clock supplying pulses at a frequency of 10 MHz can only control arbitration systems in a three processor system. Moreover, in this type of arbitration, the priority is dependent on the position of each arbitration system in the line of processors, so that the processor located at the end of the line does not function under very favourable conditions.
Parallel arbitration systems make it possible to connect a larger number of processors to a common bus to give access to common resources. In these systems, each processor has a bus access request line and a line making it possible to supply the arbitration result. Often other control lines are added to the aforementioned lines in order to give the state of the arbitration system (occupied, urgent).
Finally, in multiprocessor systems, the priorities can be treated in different ways and can be fixed, cyclic sequential or both fixed and cyclic sequential.
The actual arbitration systems can be centrallized or decentralized. A centralized arbitration system is attached to a group of processors, whilst a decentralized arbitration system is attached to each processor. A centralized system requires fewer circuits than a decentralized system, but its availability determines the availability of the multiprocessor system.
At present it would seem that the choice of the organization of a multiprocessor system is moving towards parallel arbitration systems with a fixed priority for reasons of speed, whilst the choice is moving towards arbitration systems with a series priority for reasons of simplicity. Arbitration systems for access requests to a common bus in a multiprocessor structure use both series arbitration and parallel arbitration.
In a more general manner, the arbitration systems described hereinbefore have the following disadvantages. The series arbitration system requires the use of a very fast clock to permit the connection of several processors and this leads to the development of very rapid switching components in order to make it possible to transmit on a bus signals, whose frequency is above 10 MHz. Moreover, the fixed priority of these systems leads to programming constraints for the different processors, so that the lowest priority processor may never have access to the bus. In certain multiprocessor systems, the data are transferred by blocks. The access of a processor to a common bus in this case requires the time of several exchanges with the memory, so that such systems are very costly for giving access to a memory word.
In most cases parallel arbitration systems are centralized and consequently have a limited availability. In this case the priority is often fixed in order to reduce the complexity of the arbitration system.
In general terms all the known arbitration circuits work with a clock making it possible to obviate conflicts. The presence of this clock requires a supplementary synchronization time for the different processors thereon (this time being dependent on the clock frequency). Moreover, the different processors are dependent on the clock for all availability problems.
None of the existing systems makes it possible to obtain a mixed arbitration (mixture of fixed and cyclic priorities). Finally, at present in multiprocessor systems there is no circuit permitting a supervision of the arbitration systems in such a way as to switch from one arbitration system to the other if one of them fails.